1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory apparatus in which multi-value data can be stored using memory cell transistors with floating gate electrodes.
2. Description of the Prior Art
In a programmable ROM (EEPROM: Electrically Erasable Programmable ROM) which has multiple memory cells, each comprising a single transistor, and which is capable of electrically erasing data stored in the memory cells, each memory cell comprises a double-gate transistor which has a floating gate electrode and a control gate electrode. A memory cell transistor with this type of double-gate structure writes data by accelerating hot electrons, generated on the drain region side of the control gate electrode, and injecting them into the floating gate electrode. Data is read out by detecting the difference in the operating characteristics of the memory cell transistor when electrical charge is injected at the floating gate electrode and when no charge being is injected.
FIG. 1 shows a front view of a memory cell portion of a conventional non-volatile semiconductor memory apparatus having floating gate electrodes, and FIG. 2, a cross-sectional view taken along the line X--X. These diagrams show a split gate structure wherein a portion of a control gate electrode is provided alongside a floating gate electrode.
A plurality of separate regions, comprising strips of oxide film (LOCOS) having selected thicknesses, are disposed on the surface of a P-type silicon substrate 1, the element regions being partitioned. Floating gate electrodes 4 are disposed on the silicon substrate 1, with oxide films 3 provided therebetween, so as to straddle adjacent separating regions 2. Each of the floating gate electrodes 4 is provided independently for one memory cell. And, thick oxide films 5 are disposed above the centers of the floating gate electrodes 4, at acute angles to the ends of the floating gate electrodes 4, in order to increase electromagnetic concentration at the ends of the floating gate electrodes 4 when data is erased. Control gate electrodes 6 are disposed on the silicon substrate 1, with one control gate electrode 6 corresponding to each row of multiple floating gate electrodes 4. One part of the control gate electrode 6 overlaps the floating gate electrodes 4, and the remaining part is disposed over the silicon substrate 1 with the oxide film 3 therebetween. Further, adjacent rows of floating gate electrodes 4 and control gate electrodes 6 are provided so that their surfaces are symmetrical to each other. Multiple N-type first diffusion layers 7 and N-type second diffusion layers 8 are provided in the substrate regions between the control gate electrodes 6 and the substrate regions between the floating gate electrodes 4. The first diffusion layers 7 are provided independently between the control gate electrodes 6 and are separated by the separating regions 2. By contrast, the second diffusion layers 8 continue parallel to the lengths of the control gate electrodes 6. Thus, each memory cell transistor comprises a floating gate electrode 4, a control gate electrode 6, a first diffusion layer 7 and a second diffusion layer 8. Aluminium lines 10 are provided over the control gate electrodes 6, with an oxide layer therebetween, so as to intersect with the control gate electrodes 6. The aluminium lines 10 pass through control holes 11 and connect to the first diffusion layers 7.
In a double-gate memory cell transistor of the above type, the ON resistance between the source and the drain fluctuates in accordance with the amount of charge which is injected to the floating gate electrode 4. Therefore, the ON resistances of the memory cell transistors are individually varied by injecting separate charges into the floating gate electrodes 4. The resulting differences in operating characteristics of the memory cell transistors correspond to data which are stored. For example, data of four values (equivalent to two bits) can be stored in one memory cell transistor by injecting charge to the floating gate electrode 4 in four steps and reading out the resistances of the memory cell transistor in four steps.
FIG. 3 is a circuit diagram showing the memory cell portion of FIG. 1. As FIG. 3 shows, four rows and four columns of memory cells are provided.
The control gate electrodes 6 of the double-gate memory cells 20 are connected to word lines 21, and the first diffusion layers 7 and the second diffusion layers 8 are connected to bit lines 22 and source lines 23 respectively. The bit lines 22 connect, via selective transistors 24, to a data wire 25, which is connected to a read load resistor 26. The source lines 23 connect to a power line 27. A write clock .phi.W is applied along the power line 27 to each of the source lines 23, and a read clock .phi.R is applied from the data wire 25, via the read load resistor 26, to each of the bit lines 22.
Normally, the control gate electrodes 6, which are provided along each row of memory cell transistors 20, function as the word lines 21, and the aluminium lines 10, which are connected to the first diffusion layers 7, function as the bit lines 22. Furthermore, the second diffusion layers 8, which run parallel to the control gate electrodes 6, are used as the source lines 23.
Row selecting signals LS1.about.LS4, which are based on row address data, activate specific wires of the memory cell transistors 20 by selecting one of the word lines 21.
Column selecting signals CS1.about.CS4, which are based on column address data, activate specific columns of the memory cell transistors 20 by switching one of the selective transistors 24 ON. Thus, by means of row address data and column address data, it is possible to specify any one of the multiple memory cell transistors arranged in columns and rows, and to connect the specified transistor to the data wire 25.
Data is written into the memory cell transistors 20 by injecting charge to the floating gate electrodes 4. More concretely, a ground potential (for instance, 0V) is applied from the data wire 25 to the memory cell transistors 20, while a write power potential (for instance, 12V) is applied from the power line 26 to the memory cell transistors 20. As a result, data is written (i.e. charge is injected to the floating gate electrode 4) at the memory cell transistor 20 which has been activated by the selecting signals LS1.about.LS4 and CS1.about.CS4. Also, data is read out from the memory cell transistors 20 by detecting the resistances when the memory cell transistors 20 have been switched ON. More concretely, a power potential for reading (for instance, 2V) is applied to the memory cell transistors from the data wire 25 and a ground potential (for instance, 0V) is applied to the memory cell transistors 20 from the power line 26. Here, sense amplifiers (not shown in the diagram), which are connected to each of the bit lines 22, detect the ON resistances of the memory cell transistors 20.
In order to improve recording precision when writing multi-value data (or analog data) into the memory cell transistors 20, the operations of charge injection (writing) and identification of charge amounts (reading) are performed repeatedly in short cycles. In other words, data are gradually written to the memory cell transistors 20 while simultaneously being read, and the writing ends when the data which have been read out match the contents of the data being recorded.
FIG. 4 depicts waveforms for the write clock .phi.W and the read clock .phi.R. As FIG. 4 shows, the write clock .phi.W is, for instance, set to rise only during fixed periods in a fixed cycle, and is applied to the memory cell transistors 20 from the power line 27 via the source lines 23. Then, the data wire 25 is lowered to ground potential in synchronism with the write clock .phi.W. Therefore, during the periods when the write clock .phi.W is rising, current from the source line 23 is passed through a selected memory cell transistor 20 to the bit line 22, whereby an electrical charge is injected to the floating gate electrode 4 of the selected memory cell transistor 20.
Furthermore, as FIG. 4 shows, the read clock .phi.R is, for instance, set so that the pulse rises only during the leisure times in the write clock .phi.W, and is applied to the memory cell transistors 20 from the data wire 25 via the bit lines 22. As a result, the power line 27 is lowered to ground potential in synchronism with the read clock .phi.R. Therefore, during the period when the read clock .phi.R is rising, current from the data wire 25 flows to the power line 27 through the resistor 26 and the selected memory cell transistor 20. The potential of the bit line 22, which changes in accordance with the ratio between the ON resistance of the memory cell transistor 20 and the resistance of the read load resistor 26, is read out by the sense amplifier connected to the bit line 22. The read/write cycle described above is therefore repeated until the potential read out by the sense amplifier corresponds to the value of the data to be written.
FIG. 5 is a block diagram showing the configuration of a sense amplifier for detecting the ON resistance of the memory cell transistor 20 which is connected to the bit lines 22.
As FIG. 5 shows, the sense amplifier comprises a pair of load resistors 31 and 32, a pair of current amplifiers 33 and 34, a reference transistor 35, a fixed potential generator 36, a differential amplifier 37 and a determining/controlling circuit 38. The pair of load resistors 31 and 32, which have identical resistances, connect to a power source. The pair of current amplifiers 33 and 34 each comprise a transistor and an inverter, and are connected respectively to the pair of load resistors 31 and 32, which connect to the power. The data wire 25, which the memory cell transistors 20 are selectively connected to, connects to current amplifier 33. The reference transistor 35 connects to current amplifier 34. The resistance at the reference transistor 35 is varied in response to a reference potential VRG, which is applied to the gate of the reference transistor 35. This reference potential VRG, which corresponds to multi-value data to be stored in the memory cell transistor 20, is generated and supplied to the gate of the reference transistor 35 by the fixed potential generator 36. For instance, when data of four values (equivalent to two bits) are to be stored in the memory cell transistor 20, the fixed potential generator 36 sequentially supplies three types of gate potentials VRG to the reference transistor 35, with the result that the resistance of the reference transistor 35 is altered in three steps.
The two input circuits of the differential amplifier 37 connect to the connections between pair of load resistors 31 and 32 and the pair of current amplifiers 33 and 34. The differential amplifier 37 compares the potentials VBL and VRL at each of the two connections and outputs the result of the comparison CO to the determining/controlling circuit 38. The determining/controlling circuit 38 controls the reference potential which is generated by the fixed potential generator 36. In addition, the determining/controlling circuit 38 determines the result of the comparison CO and plays back multi-bit data which corresponds to multi-value data. For instance, when determining data of four values, the upper bit is first determined by generating the middle potential of the three-step reference potentials. Then, the highest potential or the lowest potential of the three-step reference potentials is generated, in accordance the upper bit which has been determined, enabling the lower bit to be determined.
When data is read out from the memory cell transistor 20, the source side of the memory cell transistor 20 connects to ground, and the memory cell transistor 20 and the load resistor 31 are connected in series, via the current amplifier 33, at a point between the power and the ground. Similarly, the load resistor 32 and the reference transistor 35 are connected in series, via the current amplifier 34, at a point between the power and the ground. In the present case, the potential VBL at the connection between the load resistor 31 and the current amplifier 33 is determined in accordance with the ratio of the drive capabilities of load resistor 31 and memory cell transistor 20. Similarly, the potential VRL at the connection between the load resistor 32 and the current amplifier 34 is determined in accordance with the ratio of the drive capabilities of load resistor 32 and reference transistor 35. Consequently, in the case where the resistances of the reference transistor 35 are switched sequentially in steps, based on the comparison carried out by the differential amplifier 37, it is possible to determine which of these resistance regions the resistance of the memory cell transistor corresponds to. This type of sense amplifier is disclosed, for instance, in 1995 IEEE/International Solid-State Circuit Conference/Session 7/Flash Memory/Paper TA 7.7.
In the sense amplifier described above, which reads out the resistance ratio between the memory cell transistor 20 and the load resistor 31 and the resistance ratio between the reference transistor 35 and the load resistor 32, the settings of the resistances of the load resistors 31 and 32 are important. Normally, the resistances of load resistors 31 and 32 are set in accordance with the resistance of the memory cell transistor 20. When the resistances of the load resistors 31 and 32 are greater or lower than the optimum value, the change in the connection potential VBL will decrease with respect to change in the resistance of the memory cell transistor 20. In other words, when the settings of the resistances of the load resistors 31 and 32 deviate from the optimum, there is the problem that the differential amplifier 37 will not be able to correctly read out the changes in the potentials VBL and VRL at the connection points.
Furthermore, since the operating characteristics of the reference transistor 35 and the fixed potential generator 36 influence the potential VRL, which is used as the determining reference for the differential amplifier 37, it is essential that the reference transistor 35 and the fixed potential generator 36 operate with stability, so as not to adversely influence all the potentials within the operation range. However, the fixed potential generator 36 is liable to be affected by manufacturing discrepancies in the circuit configuration elements, requiring detailed adjustments and the like in order to ensure a stable supply of gate potential VRG. An increased circuit configuration is needed in order to perform these adjustments, consequently increasing the scale of the sense amplifier and eventually leading to greater manufacturing costs.